News

Design-Reuse3h
Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits
Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits View Single Port Register File compiler - Memory ...
Design-Reuse6h
14-bit, 1200 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B1P2G-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ADC ...
Design-Reuse6h
800MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
The SM-CTDSM-800M is a 12-bit continuous-time delta-sigma (CTΔΣ) analog-to-digital converter IP. By leveraging Seamless’ patented Switched-Mode Signal Processing (SMSP) technology, our ADC seamlessly ...
Design-Reuse6h
24-bit Analog fromt end (AFE) product having sigma delta ADC for weighing scale, Strain Guage, Sensor application
AFE24B19KS180NM is low-power, low noise 8-channel fully differential or 16 pseudo differential inputs, 24-bit, (ΔΣ) analog-to-digital converters (ADCs) with an integrated low-drift internal reference ...
Design-Reuse6h
40G UCIe PHY IP on Samsung SF4X
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY’s flexible ...
Design-Reuse9h
Magillem Registers System Integration Automation
Cost-effective and scalable, Magillem Registers offers a unified methodology for HW/SW Interface automation. The Registers approach targets the traditional need to manage registers efficiently for ...
Design-Reuse11h
Top-down SoC Design Methodology
Abstract: Deep sub-micron effects complicate design closure for very large designs. Top-down hierarchical design methodology combined with physical prototyping increases design productivity and ...
Design-Reuse11h
Scan Chains: PnR Outlook
At times physical design engineers find it difficult to relate with the additional timing modes introduced in PnR due to DFT insertion. These additional timing modes and related issues could be ...
Design And Reuse11h
SMIC Q2 revenues to take 6% hit due to tool maintenance and validation issues
SMIC has had trouble with yields and output which will reduce this quarter's revenues by 6%, reports DigiTimes. The problems ...
Design And Reuse11h
Rambus Delivers Industry-Leading Client Chipsets for Next-Generation AI PC Memory Modules
Expands memory chipset offering to cover all JEDEC defined memory modules for servers and PCs ...
Design-Reuse11h
Security Considerations For Bluetooth Smart Devices
Bluetooth Smart is an emerging short range wireless technology aimed for low power devices. Bluetooth 4.2 core specification provides various methods to secure the communication between devices and ...
Design-Reuse11h
Jitter Cleaner PLL Digital Loop Filter
The DPLL is a digital loop filter/controller designed to be used in conjunction with Silicon Creations Fractional-N PLLs. The resulting dual-loop PLL can attenuate jitter in extremely noisy reference ...